Pentium II ... Pentium II Xeon ...
Pentium III ... Pentium III Xeon .... arrgggh!

By: Clive "Max" Maxfield

There is currently a lot of confusion as to the plethora of processors that abound in the marketplace, so here’s a brief summary...

The Pentium Pro (introduced Nov. ‘95) evolved into the Pentium II (introduced May ‘97). The Pentium Pro was presented as a multichip module, which contained the core CPU chip and the L2 cache chip (see below for more info on "cache"), and which plugged into something called "socket 8" on the motherboard. By comparison, the Pentium II came in a single-edge-connect (SEC) cartridge, which also contained the core CPU chip and a number of L2 cache chips, and which plugged into a connector called "Slot 1" on the motherboard.

Apart from the different packaging style and its higher clocking frequencies, the Pentium II core CPU was essentially identical to the Pentium Pro core CPU, except that the Pentium II has 57 additional instructions called MMX (see below for more details on MMX).

In turn, the Pentium II evolved into the Pentium II Xeon (introduced June ‘98). The Xeon had yet another packaging style, which plugged into a connector called "Slot 2" on the motherboard. The only other significant difference between the Pentium II and the Pentium II Xeon (as far as we’re concerned) is that the Xeon’s L2 cache bus runs faster (more details below).

The Pentium II later evolved into the Pentium III, code named "Katmai" (introduced Feb ‘99). The only significant difference between these two processors (as far as we’re concerned) is that the Pentium III supports 70 additional instructions called (amongst other things) MMX II (see below).

Similarly, the Pentium III has a Pentium III Xeon counterpart, code named "Tanner" (introduced March ‘99), which also supports MMX II instructions. Again, the only significant difference between the Pentium III and the Pentium III Xeon (as far as we’re concerned) is that the Xeon’s L2 cache bus runs faster (more details below).

Cache
What do we mean by "cache"? When a program is first run and the CPU first reads an instruction or piece of data from the main memory, in addition to loading that information into the CPU itself, it also places a copy in a small, very fast, local memory called the "cache."

The next time the CPU wishes to read from that memory location, it first checks to see if there’s already a copy inside the cache. If there is, then the CPU can read this copy much, much faster than it could from the main memory.

One way to think of this is that even the largest software applications/programs are typically formed from loops containing relatively small numbers of instructions, all of which can be stored in the cache. If the cache is full and the program moves to a new block of instructions, then the least-used contents of the cache are discarded.

Today's CPUs support two levels of cache called L1 ("Level 1") cache and L2 ("Level 2") cache, respectively. The L1 cache is small (32KB on Pentium IIs and Pentium IIIs) and resides on the same silicon chip as the CPU itself. The L2 cache is larger (512KB for Pentium IIs and Pentium IIIs) and is built on additional devices. (Note that Pentium II Xeons and Pentium III Xeons offer a choice of 512KB, 1MB, and 2MB caches. The 1MB and 2MB versions are particularly well-suited for server applications.)

Commencing with the Pentium Pro, all of Intel’s processors (including the Pentium II, Pentium III, and their Xeon counterparts) have two separate buses called the "frontside bus" and the "cache bus" (the "frontside bus" may also be referred to as the "CPU bus", "host bus", or "system bus"). Note that the CPU can access both of these buses simultaneously.

As I pen these words, the Pentium II, Pentium II Xeon, Pentium III, and Pentium III Xeon all support a host bus speed of 100 MHz.

In the case of the Pentium II and Pentium III processors, the L2 cache bus runs at half the speed of the core CPU clock. That is, if the core CPU clock is 400 MHz, the L2 cache bus is 200 MHz; if the CPU clock is 500 MHz, the L2 cache bus is 250 MHz, and so forth.

By comparison, in the case of the Pentium II Xeon and Pentium III Xeon processors, the L2 cache bus runs at the full CPU clock frequency. Thus, the Xeon processors are particularly well-suited to CPU-intensive (and particularly cache-intensive) applications.

MMX Instructions
Pentium Pro, Pentium II, Pentium II Xeon, Pentium III, and Pentium III Xeon processors all have 32-bit wide internal data buses and typically manipulate data in 32-bit chunks. For example, if a programmer wishes to perform an operation such as an addition, he or she is typically obliged to add two 32-bit words together.

Certain applications, however, prefer to play with smaller pieces of data. For example, consider a 32-bit color graphics application, which uses 8-bits each to represent the red, green, blue, and alpha (translucency) values associated with each pixel (these are abbreviated to RGBA). In order to use the memory efficiently, the application stores the four 8-bit values associated with each pixel in a 32-bit word.

In these types of graphics applications, it’s common to want to perform operations like adding the RGBA values from two pixels together -- that is, to add the two 8-bit R values together, add the two 8-bit G values together, and so forth. But if the central processor can perform operations only on 32-bit words, the application is going to spend one heck of a lot of time "unpacking" (extracting) the 8-bit chunks it’s interested in, adding these chunks together, and then packing them back up again. This is the way things had to be done with the Pentium Pro (and earlier) processors.

There are many applications that wish to deal with smaller pieces of data in this fashion, so the guys and gals at Intel introduced a set of 57 MMX, which were made available in the Pentium II processor. These arithmetic and logical instructions, which are classed as SIMD (single-instruction-multiple-data) instructions, allow programmers to treat 32-bit words of data as two 16-bit chunks or four 8-bit chunks.

MMX instructions were initially conceived for the purpose of speeding up multimedia applications (which is why "MMX" actually stands for "MultiMedia eXtensions"), especially in the realm of audio and video compression and decompression algorithms implemented in software. However, these instructions are actually starting to wave a cheery "hello" and make their presence felt in a number of other applications.

MMX II Instructions
A key point about the original MMX instructions is that they only worked on integer values, which is great for some multimedia applications and certain graphics operations. but many digital media, CAD, and ViZSim applications make intensive use of floating point numbers.

Thus, the Pentium III and Pentium III Xeon processors have been augmented to contain a number of 128-bit wide internal registers. These processors also feature MMX II, which refers to an additional 70 instructions that allow the programmer to perform operations on four 32-bit floating point values simultaneously. (These instructions were also known as "Katmai New Instructions (KNI)" for a time. Then they were called "Streaming SIMD instructions" -- see the definition of SIMD above. More recently they have come to be known as SSE for "Streaming SIMD Extensions" ... and it's anyone's guess what they will be called next week!)

Copying an existing application from a Pentium II to a Pentium III will typically show no speed increase (excepting the fact that the Pentium III will have a higher clock speed) unless the graphics driver has been modified to take advantage of SSE as noted below). Recompiling the application using a Pentium III specific compiler will typically show some speed improvements.

However, in order to take full advantage of the Pentium III's SSE (or MMX II if you prefer), programmers will have to modify their applications. Similarly, graphics companies will have to modify their drivers to take advantage of the MMX II instructions (this will be of particular interest in the case of graphics cards that don't have on-board geometry accelerators). As these modifications start to take place, Pentium III-based machines will start to demonstrate significant performance advantages over their Pentium II counterparts.